With reference to the block diagram of FIG. 13, the circuit structure of a general dynamic type semiconductor memory will be explained hereinafter. The DRAM comprises, a memory cell array 1 having a plurality of memory cells storing unit memory information arranged in a matrix manner. It further comprises, as peripheral circuitry, a row-and-column address buffer 2 for receiving externally applied address signals (A.sub.0 -A.sub.9 ; in case of lMbit) for selecting a memory cell, a row decoder 3 and a column decoder 4 for specifying a memory cell by decoding the address signal, a sense refresh amplifier 5 for amplifying and reading out the signal stored in the specified memory cell, a data-in buffer 6 and a data-out buffer 7 for data input/output, and a clock generator 8 for generating clock signals .PHI.1 and .PHI.2. Clock generator 8 is implemented so as to receive row address strobe signal RAS and column address strobe signal CAS applied externally.
FIG. 14 is an equivalent circuit diagram of a memory cell forming memory cell array 1. Memory cell 9 is formed of one transfer gate transistor 10 and one capacitor 11. The gate electrode of transfer gate transistor 10 is connected to a word line 12, while one of the source/drain region is connected to a bit line 13, and the other connected to one electrode of a capacitor 11.
The DRAM stores data according to the presence or absence of a signal charge in the capacitor of the memory cell. The determination of the presence or absence of data is made by specifying each word line to select a memory cell, reading out from the bit line a small signal responsive to the presence or absence of a signal charge in the capacitor of the selected memory cell, and amplifying the same by an sense amplifier. The signal charge stored in the memory cell capacitor dissipates due to disturbance such as by leakage currents after some time passes. It will be necessary to update the stored information in each memory cell periodically in order to keep storing the data. The circuit operation for this purpose is called the refresh operation. More specifically, with reference to FIGS. 13 and 14, refresh operation is carried out by amplifying the small signal from the memory cell with a sense amplifier provided corresponding to each bit line, after selecting a word line to activate the memory cells connected to that word line, and returning the same to the memory cell. By executing the above mentioned refresh operation with respect to all word lines changing the row address sequentially, all information within the memory cell array is updated. It is necessary to repeat the refresh operation at a period shorter than the time period in which the signal charge is held in the memory cell. The shorter the hold time of the signal charge is, the greater the number of refresh operations, the so-called refresh division number.
FIG. 15 shows a sectional view of memory cell 9 of FIG. 14. Referring to FIG. 15, a thick field oxide film 15 for device isolation is formed on the surface of a semiconductor substrate 14. On the surface of semiconductor substrate 14 enclosed by field oxide film 15, transfer gate transistor 10 and capacitor 11 are formed.
Transfer gate transistor 10 is provided with a gate electrode (word line) 12 formed above the surface of semiconductor substrate 14 with a gate oxide film 16 therebetween. The circumference of gate electrode 12 is covered by a silicon oxide film 17 for insulation. Particularly, silicon oxide film 17 formed at the sides of gate electrode 12 is implemented with the so-called sidewall structure. Within semiconductor substrate 14, n.sup.- impurity regions 18a and 19a of low concentration are formed in a position self-aligning gate electrode 12. Also, n.sup.+ impurity regions 18b and 19b of high concentration are formed at a position self-aligning the sidewalls of silicon oxide film 17. The so-called LDD (Lightly Doped Drain) structure is formed by these n.sup.- impurity regions 18a and 19a and n+ impurity regions 18b and 19b. The impurity regions of this LDD structure become source/drain regions 18 and 19.
Capacitor 11 has a stacked structure constituted by a lower electrode 20 having impurities doped, a dielectric film 21 formed by silicon nitride film, silicon oxide film, or a multilayer film such as of silicon nitride film and silicon oxide film, and an upper electrode 22 formed of polysilicon having impurities doped. Capacitor 11 has the lower electrode 20 formed above gate electrode 12 of transfer gate transistor 10. A portion of lower electrode 20 is connected to one n+ source/drain region 19b of transfer gate transistor 10. Such a capacitor 11 having a structure in which a portion is formed over transfer gate transistor 10 is called a stacked capacitor, while DRAMs including such capacitors are called stacked type DRAMs.
Although not shown, MOS (Metal Oxide Semiconductor) transistors having the above mentioned LDD structure are used in the peripheral circuit.
The effect of the LDD structure of a MOS transistor will be explained hereinafter. The employment of LDD structure was due to advancement in high integration of DRAMs. The minute structure of MOS transistors associated with the high integration of DRAMs induced short channel effect, resulting in various problems. The electric field intensity in the channel region was increased because of the short channel, to generate hot carriers in the vicinity of the drain. This is trapped within the gate oxide film and generates surface level. This causes deterioration in characteristics such as threshold value voltage change and decrease of mutual conductance. A LDD structure with the n.sup.- impurity region of low concentration and n.sup.+ impurity region of high concentration formed offset was proposed to prevent change in characteristics caused by hot carriers. The n.sup.- impurity region of low concentration in the LDD structure decreases the electric field intensity to suppress the generation of hot carriers by reducing the junction grade of the pn junction. It is required that this n.sup.- impurity region of low concentration controls the diffusion width and impurity concentration precisely.
With reference to FIGS. 16A-16I, the manufacturing process of a DRAM will be explained. Such a DRAM manufacturing process is shown in Japanese Patent Application Laying-Open 63-44756, for example. For convenience of description, memory cell 9 and the CMOS transistor (complementary MOS: referred to as CMOS hereinafter) implementing a portion of the peripheral circuit is taken as an example.
As shown in FIG. 16A, field oxide film 15 is formed on the surface of semiconductor substrate 14 by LOCOS (Local Oxidation of Silicon) method. In the peripheral circuit region of semiconductor substrate 14, a p well region 23 and a n well region 24 for n channel MOS (referred to as nMOS hereinafter) and p channel MOS (referred to as pMOS hereinafter) formation implementing a CMOS are formed in advance.
As shown in FIG. 16B, a thin silicon oxide film and polysilicon layer are formed in sequence on the surface of semiconductor substrate 14. On the surface of the polysilicon layer, oxide films 17 and 27 are formed. Then, a predetermined shape is patterned using lithography and etching method. Thus, nMOS gate oxide film 16 implementing a memory cell, gate electrode 12, nMOS and pMOS gate oxide films 25a and 25b forming the peripheral circuit, and gate electrodes 26a and 26b are formed.
After a resist 29a covers the pMOS region of the peripheral circuit, phosphorus (P) ions or arsenic (As) ions 30a of low concentration are implanted onto the surface of the substrate. This ion implanting step causes n- impurity regions 18a and 19a of the transfer gate transistor 10 of the memory cell and n.sup.- impurity region 31 of the nMOS transistor of the peripheral circuit to be formed.
After an oxide film is deposited all over the substrate, this oxide film is etched anisotropically, as shown in FIG. 16D. This forms sidewalls 17a and 27a of oxide films at the sidewalls of gate electrode 12 of the transfer gate transistor 10 and gate electrode 26a of the peripheral circuit's nMOS transistor.
Using these sidewalls 17 and 27a of oxide film, n impurity ions 30b such as arsenic (As) or phosphorus (P) of high concentration are implanted onto the surface of the substrate. By this ion implantation, n+ impurity regions 18b and 19b of transfer gate transistor 10 and n.sup.+ impurity region 33 of the nMOS transistor of the peripheral circuit are formed.
According to the above mentioned steps, the LDD structure of transfer gate transistor 10 of the memory cell and the LDD structure of the nMOS transistor of the peripheral circuit are implemented.
As shown in FIG. 16E, a resist 29b covers the surface of the memory cell and the nMOS transistor region of the peripheral circuit, followed by implanting p type impurity ions 32 of high concentration such as boron (B, BF.sub.2) onto the surface of the substrate through sidewalls 27a of gate electrode 26b. By this ion implanting step, p.sup.+ impurity regions 35 and 35 of pMOS transistor are formed. Thus, the pMOS transistor of the peripheral circuit is formed by the above mentioned steps.
Next, the manufacturing steps of capacitor 11 of the memory cell will be explained. As shown in FIG. 16F, after an interlayer film 41 is deposited using CVD (Chemical Vapor Deposition) method on the surface of the substrate in which gate electrodes and the like of the transistor are formed, interlayer film 41 is patterned using lithography and etching method to form a contact region connecting lower electrode 20 of the capacitor with the substrate.
Then, as shown in FIG. 16G, polysilicon is deposited using CVD method. It is necessary to dope n type impurities for polysilicon to possess electrical conductivity. This is implemented by doping with gas such as phosphine (PH.sub.3) at the time of the CVD step, or by implanting and driving-in phosphorus (P) or arsenic (As) using ion implanting method after the deposition of polysilicon or after a predetermined patterning. Then, lower electrode 20 of capacitor 11 is formed by patterning this polysilicon layer.
As shown in FIG. 16H, a capacitor dielectric film 21 formed of silicon nitride film, silicon oxide film, or a composite film of these is formed using the CVD method. A doped polysilicon layer 22 is deposited thereof using CVD method. Then, patterning of a predetermined shape is carried out using photolithography and etching method. Thus, capacitor 11 is formed.
As shown in FIG. 16I, interlayer insulating film 40 is formed above the surface of the substrate where devices such as transistors and capacitors are formed, followed by opening a predetermined region to form bit line 13.
After the formation of a second interlayer insulating film 42, a predetermined region is opened to form a wiring layer 43.
Thus, a DRAM is manufactured comprising a transistor having the LDD structure, in accordance with the above mentioned steps.
As set forth throughout the above description, transfer gate transistor 10 of the memory cell in a conventional DRAM has source/drain regions 18 and 19 of the LDD structure formed by ion implantation. When n+ impurity regions 18b and 19b of high concentration are formed by ion implanting method, many crystal deficiencies are generated on the surface of the semiconductor substrate 14. The crystal deficiencies are recovered to some extent by a later heat processing for activation, but not completely. In the case where lower electrode 20 of capacitor 11 is formed over source/drain region 19 where crystal deficiencies remain, signal charge stored in capacitor 11 passes through the crystal deficiencies within source/drain region 19 flowing to the substrate side to generate leakage currents. Due to the reduction in capacitor capacitance associated with the miniaturization of the device structure in recent years, the disappearance of signal charge by leakage currents from the capacitor became a large problem. Therefore, the hold time of signal charge stored in memory cells becomes shorter, leading to problems such as the need to increase the number of refresh operations.
There was also a problem of poor contact between substrate 14 and bit line 13 or lower electrode 20 of capacitor 11. This was ascribed to multiple oxidization of incidental oxide film by impurity effect, generated on the surface of semiconductor substrate 14 where impurity regions 18b and 19b of high concentration are formed, caused by air entering the CUD chamber when the semiconductor is introduced into the chamber.
An approach to suppress the occurrence of leakage currents from the capacitor is shown in Japanese Patent Laying-Open No. 64-80065. FIG. 17 is a sectional structure view of the DRAM shown in the above mentioned laid-open application. Referring to FIG. 17, a sectional structure of a memory cell array and the peripheral circuit devices are shown. On p type silicon substrate 14, p well region 14a and n well region 14b are formed. The memory cell array and nMOS transistor 100 of the peripheral circuit are formed in p well region 14a, whereas pMOS transistor 110 is formed in n well region 14b. The memory cell constituting the memory cell array is constructed of one transfer gate transistor 10 and one capacitor 11, similar to the memory cell of FIG. 15. Comparing the structures of the second conventional memory cell of FIG. 17 and the first conventional memory cell of FIG. 15, the transfer gate transistor 10 of the second conventional memory cell has the so-called LDD structure with n.sup.- impurity region 19a of low concentration formed by ion implantation of source/drain region 19 of the side connected to capacitor 11 and n.sup.+ impurity region 19b of high concentration formed by impurity heat diffusion from lower electrode 20 of capacitor 11. The source/drain region 18 of the side connected to bit line 13 has the LDD structure with n.sup.- impurity region 18a of low concentration formed by ion implantation and n.sup.+ impurity region 18b of high concentration formed also by ion implantation. The transfer gate transistor 10 of this example suppresses the generation of crystal deficiency in the surface of the substrate by ion implantation to decrease the generation of leakage currents from the capacitor, by forming high concentration impurity region 19b without using the ion implantation method over source/drain region 19 of the side connected to the capacitor.
Bit line 13 is constituted by a three layer structure stacking a barrier metal layer 13a, an aluminum layer 13b, and a protection film 13c in sequence. Barrier metal layer 13a is formed of a refractory metal silicide layer , such as MoSi.sub.2 or the like and a refractory metal layer to prevent monocrystal silicon from being precipitated in the contact between aluminum layer 13b and source/drain region 18.
On the right hand of FIG. 17, a sectional structure view of a CMOS implementing the peripheral circuit is shown. The nMOS transistor 100 of the CMOS is constructed of a gate insulating film 101, a gate electrode 102, and a pair of source/drain regions 103 and 104. Each of source/drain regions 103 and 104 have a LDD structure formed of n.sup.- impurity regions 103a and 104a of low concentration and n.sup.+ impurity regions 103b and 104b of high concentration. On source/drain regions 103 and 104, n.sup.+ impurity regions 103c and 104c are formed. The n impurity regions 103c and 104c are provided for the purpose of preventing source/drain regions 103 and 104 from shorting with wiring layers 105 and 105.
The pMOS transistor 110 of the CMOS is implemented by a gate insulating film 111, a gate electrode 112, and a pair of source/drain regions 113 and 114. Each of source/drain regions 113 and 114 has a LDD structure with p impurity regions 113a and 114a of low concentration and p.sup.+ impurity regions 113b and 114b of high concentration.
The main steps of manufacturing the source/drain region of the transfer gate transistor of the memory cell, which is a feature of the conventional example will be explained hereinafter. FIGS. 18A-18D are sectional views illustrating the main manufacturing steps of the DRAM of FIG. 17.
FIG. 18A shows the ion implanting steps for forming sources/drains of transfer gate transistor 10 of the memory cell and nMOS transistor 100 of the peripheral circuit. Referring to FIG. 18A, a resist 120 covers the formation region of pMOS transistor 110, followed by ion implantation of phosphorus (P) or arsenic (As) under the conditions of dosage of 10.sup.13 /cm.sup.2, and implant energy of 60-120 keV. This results in the formation of n impurity regions 18a and 19a of low concentration of transfer gate transistor 10 and n impurity regions 103a and 104a of nMOS transistor 100.
Referring to FIG. 18B, resist 120 is removed, and resist 121 covers the memory cell array and nMOS transistor 100 formation region of the peripheral circuit. Then, ion implantation of BF.sub.2 or B is carried out onto p type semiconductor substrate 14 with a dosage of 10.sup.13 /cm.sup.2 and implant energy of 60-100 keV. This results in the formation of p impurity regions 113a and 114a of low concentration of pMOS transistor 110.
With reference to FIG. 18C, the formation step of high concentration impurity region of transfer gate transistor 10 will be described hereinafter. On the surface of n.sup.- impurity region 19a of transfer gate transistor 10, lower electrode 20 of capacitor 11 is formed. Ion implantation of arsenic or phosphorus is carried out onto lower electrode 20 of capacitor 11 with a dosage of 10.sup.153 /cm.sup.2 and implant energy of 75-85 keV. Then, the n type impurities introduced into lower electrode 20 are diffused to the surface of p type silicon substrate 14 by heat processing. This diffusion step causes n+ impurity region 19b of high concentration of source/drain region 19 to be formed.
FIG. 18D shows the formation step of the high concentration region of source/drain region 18 of the transfer gate transistor. In the memory cell array, interlayer insulating layer 122 is formed above the memory cell. Interlayer insulating layer 122 has a contact hole 123 formed contacting source/drain region 18 of transfer gate transistor 10. Under this state, resist 124 covers the formation region of pMOS transistor 110 of the peripheral circuit. Then, arsenic ions are implanted into the surface of p type silicon substrate 14 at a dosage of 10.sup.15 /cm.sup.2 and implant energy of 110-130 keV. This results in the formation of n.sup.+ impurity region 18b of high concentration of source/drain region 18 of transfer gate transistor 10. Simultaneously, n.sup.+ impurity regions 103c and 104c of high concentration are formed in nMOS transistor 100 of the peripheral circuit.
Thus, in the second conventional DRAM, the source/drain region 19 of the side connected to the capacitor of transfer gate transistor 10 is constituted by a LDD structure with n.sup.- impurity region 19a of low concentration by ion implantation and n.sup.+ impurity region 19b of high concentration by heat diffusion. The source/drain region 18 of the side connected to bit line 13 is implemented by a LDD structure with n.sup.- impurity region 18a of low concentration also by ion implantation and n.sup.+ impurity region 18b of high concentration also by ion implantation.
In the above mentioned second conventional example, a method is proposed where high concentration region of source/drain region of the transfer gate transistor is formed by heat diffusion from the lower electrode of the capacitor, for the purpose of suppressing the generation of leakage currents from the capacitor caused by deficiency of the surface of the substrate due to high concentration ion implantation. However, the deleterious effect of high temperature heat processing becomes significant in proportion to the increase of the DRAM's stored capacitance such as to 16 Mb or 64 Mb, and is not preferable. That is to say, miniaturization in the structure of a memory cell array is required to increase the integration density of DRAMs. As a result, the channel length of transfer gate transistor 10 of the memory cell is minimized. If source/drain regions 18 and 19 are formed using heating process of high temperature, as in the above-mentioned second conventional embodiment, under such circumstances impurities are diffused into the channel region of transfer gate transistor 10 which results in significant short channel effect. This short channel effect will cause deterioration in the characteristics of the transistor, such as reduction in reliability lifetime of transfer gate transistor 10. Therefore, the recent technical developments in the manufacturing methods of DRAMs are carried out to shift from high temperature processes to low temperature processes. The conventional method of forming a source/drain region of high concentration in a transfer gate transistor by thermal diffusion causes short channel effect in the MOS transistor of a DRAM to impede increase in integration density of a DRAM.
In the second conventional example, n.sup.+ impurity region 18b of high concentration is formed by ion implantation on the source/drain region 18 of the side connected to the bit line. This promotes the generation of incidental oxide film as stated before, leading to a problem of preventing efficient ohmic contact between the bit line and source/drain region 18.